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general description the ds8005 dual smart card interface is a low-cost, dual analog front-end for an ic card reader interface that needs to communicate with two smart cards in a mutually exclusive fashion. the analog interface is designed for use in iso 7816, emv , and b-cas appli- cations. the device is functionally similar to two ds8024s with external multiplexing to select the active interface, but also includes low power and 1.8v card support. additionally, the device is designed for appli- cations where the c4/c8 (aux1/aux2) contacts are not required on either card interface. the device is provided in a 28-pin so package. the pinout is backwards compatible with the ds8313, allowing applications to use the same footprint and pcb for applications that communicate with either one or two smart cards. the device is designed to be used with microcon- trollers that contain an iso 7816 uart, or have the bandwidth to run this protocol in software by bit-bang- ing io ports. if the microcontroller does not have the capability of running the iso 7816 uart, the ds8007 is the more appropriate product selection. applications set-top box conditional access telecommunications pay television access control financial terminals features ? analog interface and level shifting for ic card communication ? ?kv (min) esd (hbm) protection on card interfaces ? ultra-low stop-mode current, less than 10na typical ? internal ic card supply-voltage generation 5.0v ?%, 80ma (max) 3.0v ?%, 65ma (max) 1.8v ?0%, 30ma (max) ? automatic card activation and deactivation controlled by dedicated internal sequencer ? i/o lines from host directly level shifted for smart card communication ? flexible card clock generation, supporting external crystal frequency divided by 1, 2, 4, or 8 ? high-current, short-circuit and high-temperature protection ? low active-mode current ? internal multiplexing allows one iso 7816 uart implementation to control two smart card sockets ds8005 smart card interface ________________________________________________________________ maxim integrated products 1 ordering information 19-5257; rev 0; 4/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package DS8005-RRX+ -40 c to +85 c 28 so + denotes a lead(pb)-free/rohs-compliant package. typical application circuit appears at end of data sheet. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of a ny device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . emv is a registered trademark of emvco llc. selector guide part card voltages supported low stop-mode power low active- mode power pres_ polarity v dda inputs DS8005-RRX+ 1.8v, 3v, 5v yes yes positive 2
ds8005 smart card interface 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted. all specifications apply to the device, unless otherwise noted in the conditions column.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v dd relative to gnd ...............-0.5v to +6.5v voltage range on v dda relative to gnd .............-0.5v to +6.5v voltage range on clka, rsta, i/oa ......-0.5v to (v cca + 0.5v) voltage range on clkb, rstb, i/ob ......-0.5v to (v ccb + 0.5v) voltage range on all other pins relative to gnd.......................................-0.5v to (v dd + 0.5v) maximum junction temperature .....................................+125? maximum power dissipation range (t a = -25? to +85?)..700mw storage temperature range ............................-55? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units power supply digital supply voltage v dd 2.7 6.0 v card voltage-generator supply voltage v dda must be v dd 4.75 6.0 v v th2 threshold voltage (falling) 2.20 2.45 2.65 v reset voltage thresholds v hys2 hysteresis 50 100 200 mv current consumption active v dd current 5v cards (including 80ma draw from 5v card) i dd_50v i cc = 80ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v 80.75 85 ma active v dd current 5v cards (current consumed by device only) i dd_ic i cc = 80ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v (note 2) 0.75 5 ma active v dd current 3v cards (including 65ma draw from 3v card) i dd_30v i cc = 65ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v 65.75 70 ma active v dd current 3v cards (current consumed by device only) i dd_ic i cc = 65ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v (note 2) 0.75 5 ma active v dd current 1.8v cards (including 30ma draw from 1.8v card) i dd_18v i cc = 30ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v 30.75 40 ma active v dd current 1.8v cards (current consumed by device only) i dd_ic i cc = 30ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v (note 2) 0.75 5 ma inactive-mode current i dd card inactive, active-high pres_, device not in stop mode 50 400 a stop-mode current i dd_stop device in ultra-low-power stop mode ( cmdvcc , 5v/ 3v , and 1_8v set to logic 1) (note 3) 0.01 2 a
ds8005 smart card interface _______________________________________________________________________________________ 3 recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted. all specifications apply to the device, unless otherwise noted in the conditions column.) (note 1) parameter symbol conditions min typ max units clock source crystal frequency f xtal external crystal (note 1) 0 20 mhz f xtal1 (note 1) 0 20 mhz v il_xtal1 low-level input on xtal1 -0.3 0.3 x v dd xtal1 operating conditions v ih_xtal1 high-level input on xtal1 0.7 x v dd v dd + 0.3 v external capacitance for crystal c xtal1 , c xtal2 15 pf internal oscillator f int 2.2 2.7 3.4 mhz shutdown temperature shutdown temperature t sd +150 c rsta and rstb pins output low voltage v ol_rst1 i ol_rst = 1ma 0.3 v card-inactive mode output current i ol_rst1 v ol_rst = 0v -1 ma output low voltage v ol_rst2 i ol_rst = 200a 0.3 v output high voltage v oh_rst2 i oh_rst = -200a v cc - 0.5 v rise time t r_rst c l = 30pf (note 1) 0.1 s fall time t f_rst c l = 30pf (note 1) 0.1 s current limitation i rst(limit) -20 +20 ma card-active mode rstin to rst delay t d(rstin-rst) 2 s clka and clkb pins output low voltage v ol_clk1 i olclk = 1ma 0.3 v card-inactive mode output current i ol_clk1 v olclk = 0v -1 ma output low voltage v ol_clk2 i olclk = 200a 0.3 v output high voltage v oh_clk2 i ohclk = -200a v cc - 0.5 v rise time t r_clk c l = 30pf (notes 1, 4) 8 ns fall time t f_clk c l = 30pf (notes 1, 4) 8 ns current limitation i clk(limit) -75 +75 ma clock frequency f clk operational 0 10 mhz duty factor c l = 30pf 45 55 % card-active mode slew rate sr c l = 30pf (note 1) 0.2 v/ns v cca and v ccb pins output low voltage v cc1 i cc = 1ma 0.3 v card-inactive mode output current i cc1 v cc = 0v 0 -1 ma
ds8005 smart card interface 4 _______________________________________________________________________________________ recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted. all specifications apply to the device, unless otherwise noted in the conditions column.) (note 1) parameter symbol conditions min typ max units device: i cc(5v) < 30ma, v dda = 4.75v (note 1) 4.65 5 5.25 device: i cc(5v) < 80ma 4.75 5 5.25 device: i cc(3v) < 65ma 2.78 3 3.24 device: i cc(1.8v) < 30ma 1.64 1.8 1.98 5v card; current pulses of 40nc with i < 200ma, t < 400ns, f < 20mhz 4.6 5.4 3v card; current pulses of 24nc with i < 200ma, t < 400ns, f < 20mhz 2.75 3.25 output low voltage v cc2 1.8v card; current pulses of 12nc with i < 200ma, t < 400ns, f < 20mhz 1.62 1.98 v v cc(5v) = 0 to 5v -80 v cc(3v) = 0 to 3v -65 output current i cc2 v cc(1.8v) = 0 to 1.8v -30 ma shutdown current threshold i cc(sd) (note 1) 120 ma card-active mode slew rate v ccsr up/down; c < 300nf (note 5) 0.05 0.16 0.22 v/s data lines (i/o_ and i/oin) i/o_ i/oin falling edge delay t d(io-ioin) (note 1) 200 ns pullup pulse active time t pu (note 1) 100 ns maximum frequency f iomax 1 mhz input capacitance c i 10 pf i/oa and i/ob pins output low voltage v ol_io1 i ol_io = 1ma 0.3 v output current i ol_io1 v ol_io = 0v 0 -1 ma card-inactive mode internal pullup resistor r pu_io to v cc 6 11 19 k output low voltage v ol_io2 i ol_io = 1ma 0.3 v i oh_io = < -20a 0.8 x v cc output high voltage v oh_io2 i oh_io = < -40a (3v/5v) 0.75 x v cc v output rise/fall time t ot c l = 30pf (note 1) 0.1 s input low voltage v il_io -0.3 +0.8 card-active mode input high voltage v ih_io 1.5 v cc v
ds8005 smart card interface _______________________________________________________________________________________ 5 recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted. all specifications apply to the device, unless otherwise noted in the conditions column.) (note 1) parameter symbol conditions min typ max units input low current i il_io v il_io = 0v 700 a input high current i ih_io v ih_io = v cc -20 +20 a input rise/fall time t it 1.2 s card-active mode current limitation i io(limit) c l = 30pf -15 +15 ma i/oin pin output low voltage v ol i ol = 1ma 0.3 v output high voltage v oh i oh < -40a 0.75 x v dd v dd + 0.1 v output rise/fall time t ot c l = 30pf, 10% to 90% 0.1 s input low voltage v il -0.3 +0.3 x v dd v input high voltage v ih 0.7 x v dd v dd + 0.3 v input low current i il_io v il = 0v 700 a input high current i ih_io v ih = v dd -10 +10 a input rise/fall time t it v il to v ih 1.2 s integrated pullup resistor r pu pullup to v dd 6 11 19 k control pins (clkdiv1, clkdiv2, cmdvcc , rstin, 5v/ 3v , 1_8v) input low voltage v il -0.3 +0.3 x v dd v input high voltage v ih 0.7 x v dd v dd + 0.3 v input low current i il_io 0 < v il < v dd -5 +5 a input high current i ih_io 0 < v ih < v dd -5 +5 a interrupt output pins ( off and off2 ) output low voltage v ol i ol = 2ma 0.3 v output high voltage v oh i oh = -15a 0.75 x v dd v integrated pullup resistor r pu pullup to v dd 12 24 38 k presa and presb pins input low voltage v il_pres 0.3 x v dd v input high voltage v ih_pres 0.7 x v dd v input low current i il_pres v il_pres = 0v -5 +5 a input high current i ih_pres v ih_pres = v dd 10 a
ds8005 smart card interface 6 _______________________________________________________________________________________ recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted. all specifications apply to the device, unless otherwise noted in the conditions column.) (note 1) parameter symbol conditions min typ max units timing activation time t act 50 160 220 s deactivation time t deact 50 80 100 s window start t 3 50 95 130 clk_ to card start time window end t 5 140 160 220 s pres debounce time t debounce 5 8 11 ms note 1: operation guaranteed at -40? and +85? but not tested. note 2: i dd_ic measures the amount of current used by the device to provide the smart card current minus the load. note 3: stop mode is enabled by setting cmdvcc , 5v/ 3v , and 1_8v to a logic-high. note 4: parameters are guaranteed to meet all iso 7816, gsm11-11, and emv 2000 requirements. for the 1.8v card, the maximum rise and fall time is 10ns. note 5: parameter is guaranteed to meet all iso 7816, gsm11-11, and emv 2000 requirements. for the 1.8v card, the minimum slew rate is 0.05v/? and the maximum slew rate is 0.5v/?.
ds8005 smart card interface _______________________________________________________________________________________ 7 pin description pin name function 1, 2 clkdiv1, clkdiv2 clock divider. determines the divided-down input clock frequency (presented at xtal1 or from a crystal at xtal1 and xtal2) on the clk_ output pin. dividers of 1, 2, 4, and 8 are available. 3 5v/ 3v 5v/3v selection pin. allows selection of 5v or 3v for communication with an ic card. logic-high selects 5v operation; logic-low selects 3v operation. the 1_8v pin overrides the setting on this pin if active. see table 3 for a complete description of choosing card voltages. 4 1_8v 1.8v operation selection. this active-high input puts the device into 1.8v smart card communication mode. the selected interface (when activated) powers a card with a 1.8v supply and all i/o lines operate at 1.8v. 5 v ccb smart card supply voltage, interface b. decouple to cgnd (card ground) with 2 x 100nf or 100 + 200nf capacitors (esr < 100m ). 6 v dda smart card interface supply. 5v power supply for powering the card interface. 7 rstb smart card reset, interface b. card reset output from contact c2. 8 clkb smart card clock, interface b. card clock, contact c3. 9, 14 cgnd smart card ground 10 presa interface a card presence indicator. active-high card presence input for the first card interface. when the presence indicator becomes active, a debounce tim eout begins. after 8ms (typ), the off signal becomes active if the first card interface is selected (sel_ab low), else the off2 signal becomes active. 11 i/oa smart card data-line output, interface a. card data communication line, contact c7. this pin is only active if the first card interface is selected (sel_ab low) and the interface has gone through an activation sequence. 1_8v 28 27 26 25 24 23 22 sel_ab off2 i/oin xtal2 top view xtal1 off gnd 21 v dd 20 rstin 19 cmdvcc 18 v dda2 17 v cca 16 rsta 15 clka 5v/3v clkdiv2 clkdiv1 rstb v dda clkb cgnd presa i/oa i/ob presb 4 1 2 3 5 6 7 8 9 10 11 12 13 14 cgnd v ccb so ds8005 pin configuration
ds8005 smart card interface 8 _______________________________________________________________________________________ pin description (continued) pin name function 12 i/ob smart card data-line output, interface b. card data communication line, contact c7. this pin is only active if the second card interface is selected (sel_ab high) and the interface has gone through an activation sequence. 13 presb interface b card presence indicator. active-high card presence input for the second card interface. when the presence indicator becomes active, a debounce tim eout begins. after 8ms (typ), the off signal becomes active if the second card interface is selected (sel_ab high), else the off2 signal becomes active. 15 clka smart card clock, interface a. card clock, contact c3. 16 rsta smart card reset, interface a. card reset output from contact c2. 17 v cca smart card supply voltage, interface a. decouple to cgnd (card ground) with 2 x 100nf or 100 + 220nf capacitors (esr < 100m ). 18 v dda2 smart card interface supply. 5v power supply for powering the card interface. while this pin is not required to be connected to 5v (it can be left not connected (n.c.)), it is recommended for the best performance when delivering power to a 5v smart card. 19 cmdvcc activation sequence initiate. active-low input from host. 20 rstin card reset input. reset input from the host. 21 v dd supply voltage 22 gnd digital ground 23 off status output for selected interface. active-low interrupt output to the host. includes a 20k integrated pullup resistor to v dd . this pin reflects fault events and pres_ events on the currently selected interface only (behaving as if it were a ds8024 with only one interface). the off2 pin should be used to monitor presence events on the nonselected interface. 24, 25 xtal1, xtal2 crystal/clock input. connect an input from an external clock to xtal1 or connect a crystal across xtal1 and xtal2. 26 i/oin i/o input. host-to-interface chip data i/o line. 27 off2 status output for nonselected interface. this pin passes through the presence signal for the nonselected interface. if sel_ab is low (the a interface is selected), this pin reflects the state of the presb input. if sel_ab is high (the b interface is selected), this pin reflects the state of the presa input. 28 sel_ab interface selection. this pin selects the interface the input pins (i/oin, rstin, etc.) communicate with and control. if sel_ab is low, the a interface is selected. activation sequences power up v cca and communication occurs with clka, i/oa, and rsta. if sel_ab is high, the b interface is selected. both interfaces can be powered and clocking at the same time. see the switching a/b interfaces section for more information.
ds8005 smart card interface _______________________________________________________________________________________ 9 ds8005 clock generation clkdiv1 clkdiv2 xtal1 xtal2 i/oa cgnd v cca rsta clka presa card interface b i/ob v ccb rstb v dd gnd clkb presb regulator card interface a 1_8v 5v/3v v dda v dda2 i/o xcvr rstin i/oin control sequencer sel_ab qsel_ab qsel_ab cmdvcc interrupt generation fault detection power supply off off2 figure 1. functional diagram detailed description the ds8005 is an analog front-end for communicating with 1.8v, 3v, and 5v dual smart cards. it is a dual input-voltage device, requiring one supply to match that of a host microcontroller and a separate +5v sup- ply for generating correct smart card supply voltages. the device translates all communication lines to the correct voltage level and provides power for smart card operation. it is a low-power device, consuming very lit- tle current in active-mode operation (during a smart card communication session), and is suitable for use in battery-powered devices such as laptops and pdas, consuming only 10na in stop mode. the device is designed for applications that do not require communi- cation using the c4 and c8 card contacts (aux1 and aux2). it is suitable for sim/sam interfacing, as well as for applications where only the i/o line is used to com- municate with a smart card. power supply the device has dual supplies. the supply pins for the device are v dd , gnd, and v dda . v dd should be in the 2.7v to 6.0v range, and is the supply for signals that interface with the host controller. it should, therefore, be the same supply as used by the host controller. all smart card contacts remain inactive during power-on or power-off. the internal circuits are kept in the reset state until v dd reaches v th2 + v hys2 and for the dura- tion of the internal power-on reset pulse, t w . a deacti- vation sequence is executed when v dd falls below v th2 . an internal regulator generates the 1.8v, 3v, or 5v card supply voltage (v cc_ ). the regulator should be sup- plied separately by v dda . v dda should be connected to a minimum 4.75v supply to provide the correct sup- ply voltage for 5v smart cards.
voltage supervisor the voltage supervisor monitors the v dd supply. a 220? reset pulse (t w ) is used internally to keep the device inactive during power-on or power-off of the v dd supply. see figure 2. the ic card interface remains inactive regardless of the levels on the command lines until duration t w after v dd has reached a level higher than v th2 + v hys2 . when v dd falls below v th2 , the device executes a card deactivation sequence if the card interface is active. clock circuitry the card clock signal (clka/clkb) is derived from a clock signal input to xtal1 or from a crystal operating at up to 20mhz connected between xtal1 and xtal2. the output clock frequency of clk_ is selectable through inputs clkdiv1 and clkdiv2. the clk signal frequency can be f xtal , f xtal /2, f xtal /4, or f xtal /8. see table 1 for the frequency generated on the clk_ signal given the inputs to clkdiv1 and clkdiv2. note that clkdiv1 and clkdiv2 must not be changed simultaneously; a delay of 10ns minimum between changes is needed. the minimum duration of any state of clk_ is eight periods of xtal1. the frequency change is synchronous: during a transi- tion of the clock divider, no pulse is shorter than 45% of the smallest period, and the first and last clock pulses about the instant of change have the correct width. when changing the frequency dynamically, the change is effective for only eight periods of xtal1 after the command. the f xtal duty factor depends on the input signal on xtal1. to reach a 45% to 55% duty factor on clk_, xtal1 should have a 48% to 52% duty factor with tran- sition times less than 5% of the period. with a crystal, the duty factor on clk_ can be 45% to 55% depending on the circuit layout and on the crystal characteristics and frequency. in other cases, the duty factor on clk_ is guaranteed between 45% and 55% of the clock period. i/o transceivers i/o_ and i/oin are pulled high with an 11k resistor (i/o_ to v cc_ and i/oin to v dd ) in the inactive state. the first side of the transceiver to receive a falling edge becomes the master. when a falling edge is detected (and the master is decided), the detection of falling edges on the line of the other side is disabled; that side then becomes a slave. after a time delay t d(edge) , an n transistor on the slave side is turned on, thus transmit- ting the logic 0 present on the master side. when the master side asserts a logic 1, a p transistor on the slave side is activated during the time delay t pu and then both sides return to their inactive (pulled up) states. this active pullup provides fast low-to-high tran- sitions. after the duration of t pu , the output voltage depends only on the internal pullup resistor and the ds8005 smart card interface 10 ______________________________________________________________________________________ v dd alarm (internal signal) power on t w t w power off v th2 + v hys2 v th2 supply dropout figure 2. voltage supervisor behavior table 1. clock frequency selection clkdiv1 clkdiv2 f clk 0 0 f xtal /8 0 1 f xtal /4 1 1 f xtal /2 1 0 f xtal
ds8005 smart card interface ______________________________________________________________________________________ 11 load current. current to and from the card i/o lines is limited internally to 15ma. the maximum frequency on these lines is 1mhz. inactive mode the device powers up with the card interface in the inactive mode. minimal circuitry is active while waiting for the host to initiate a smart card session. all card contacts are inactive (approximately 200 to gnd). the i/oin pin in the high-impedance state (11k pullup resistor to v dd ). voltage generators are stopped. xtal oscillator is running (if included in the device). voltage supervisor is active. the internal oscillator is running at its low frequency. activation sequence after power-on and the reset delay, the host microcon- troller can monitor card presence with signals off and cmdvcc , as shown in table 2. if the card is in the reader (if pres_ is active), the host microcontroller can begin an activation sequence (start a card session) by pulling cmdvcc low. the following events form an activation sequence (figure 3): 1) cmdvcc is pulled low. 2) the internal oscillator changes to high frequency (t 0 ). 3) the voltage generator is started (between t 0 and t 1 ). atr cmdvcc rst_ rstin clk_ v cc_ i/o_ i/oin t 0 t 1 t 2 t 3 t 4 t 5 = t act figure 3. activation sequence using rstin and cmdvcc table 2. card presence indication sel_ab off cmdvcc status low high high card a present. low low high card a not present. high high high card b present. high low high card b not present. sel_ab off2 cmdvcc status low high high card b present. low low high card b not present. high high high card a present. high low high card a not present.
ds8005 4) v cc_ rises from 0 to 5v, 3v, or 1.8v with a controlled slope (t 2 = t 1 + 1.5 t). t is 64 times the internal oscillator period (approximately 25?). 5) i/o_ pin is enabled (t 3 = t 1 + 4t) (they were previ- ously pulled low). 6) the clk_ signal is applied to the c3 contact (t 4 ). 7) rst_ is enabled (t 5 = t 1 + 7t). to apply the clock to the card interface: 1) set rstin high. 2) set cmdvcc low. 3) set rstin low between t 3 and t 5 ; clk_ now starts. 4) rst_ stays low until t 5 , then rst becomes the copy of rstin. 5) rstin has no further effect on clk_ after t 5 . if the applied clock is not needed, set cmdvcc low with rstin low. in this case, clk_ starts at t 3 (minimum 200ns after the transition on i/o; see figure 4); after t 5 , rstin can be set high to obtain an answer to request (atr) from an inserted smart card. do not perform acti- vation with rstin held permanently high. active mode when the activation sequence is completed, the card interface is in active mode. the host microcontroller and the smart card exchange data on the i/o lines. deactivation sequence when a session is completed, the host microcontroller sets the cmdvcc line high to execute an automatic deactivation sequence and returns the card interface to the inactive mode (figure 5). 1) rst_ goes low (t 10 ). 2) clk_ is held low (t 12 = t 10 + 0.5 t) where t is 64 times the period of the internal oscillator (approxi- mately 25?). 3) i/o_ pin is pulled low (t 13 = t 10 + t). 4) v cc starts to fall (t 14 = t 10 + 1.5 t). 5) when v cc_ reaches its inactive state, the deactiva- tion sequence is complete (at t de ). 6) all card contacts become low impedance to gnd; i/oin remains at v dd (pulled up through an 11k resistor). 7) the internal oscillator returns to its lower frequency. v cc generator each v cc_ generator has a capacity to supply up to 80ma continuously at 5v, 65ma at 3v, and 30ma at 1.8v. an internal overload detector triggers at approxi- mately 120ma. current samples to the detector are fil- tered. this allows spurious current pulses (with a duration of a few ?) up to 200ma to be drawn without causing deactivation. the average current must stay below the specified maximum current value. to main- tain v cc voltage accuracy, a 100nf capacitor (with an esr < 100m ) should be connected to cgnd and placed near the v cc_ pin, and a 100nf or 220nf capacitor (220nf is the best choice) with the same esr should be connected to cgnd and placed near the smart card reader? c1 contact. fault detection the following fault conditions are monitored: short-circuit or high current on v cc_ removal of a card during a transaction ? dd dropping card voltage generator operating out of the specified values (v dda too low or current consumption too high) overheating there are two different cases (figure 6): cmdvcc high outside a card session. output off_ is low if a card is not in the card reader and high if a card is in the reader. the v dd supply is mon- itored? decrease in input voltage generates an internal power-on reset pulse but does not affect the off_ signal. short-circuit and temperature detection is disabled because the card is not powered up. cmdvcc low within a card session. output off_ goes low when a fault condition is detected, and an emergency deactivation is performed automatically (figure 7). when the system controller resets cmd- vcc to high, it may sense the off_ level again after completing the deactivation sequence. this distin- guishes between a card extraction and a hardware problem ( off_ goes high again if a card is present). depending on the connector? card-present switch (normally closed or normally open) and the mechani- cal characteristics of the switch, bouncing can occur on the pres_ signals at card insertion or withdrawal. the device has a debounce feature with an 8ms typical duration (figure 6). when a card is inserted, output off_ goes high after the debounce time delay. when the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on pres_ and output off_ goes low. smart card interface 12 ______________________________________________________________________________________
ds8005 smart card interface ______________________________________________________________________________________ 13 atr cmdvcc rst_ rstin clk_ v cc_ i/o_ i/oin t 0 t 1 t 2 t 3 t 4 t 5 = t act 200ns figure 4. activation sequence at t 3 rst_ clk_ v cc_ cmdvcc i/o_ t 10 t de t 12 t 13 t 14 t 15 figure 5. deactivation sequence
ds8005 smart card interface 14 ______________________________________________________________________________________ debounce debounce v cc_ pres_ off_ deactivation caused by card withdrawal deactivation caused by short circuit cmdvcc figure 6. behavior of pres_, off_ , cmdvcc , and v cc_ rst_ clk_ v cc_ pres_ off_ i/o_ t 10 t de t 12 t 13 t 14 t 15 figure 7. emergency deactivation sequence (card extraction)
ds8005 smart card interface ______________________________________________________________________________________ 15 stop mode (low-power mode) a low-power state, stop mode, can be entered by forc- ing the cmdvcc , 5v/ 3v , and 1_8v input pins to a logic-high state. stop mode can only be entered when the smart card interface is inactive. in stop mode, all internal analog circuits are disabled. the off_ pin fol- lows the status of the pres_ pin. to exit stop mode, change the state of one or more of the three control pins to a logic-low. an internal 220? (typ) power-up delay and the 8ms pres_ debounce delay are in effect and off_ is asserted to allow the internal circuitry to stabilize. this prevents smart card access from occur- ring after leaving stop mode. figure 8 shows the control sequence for entering and exiting stop mode. note that an in-progress deactivation sequence always finishes before the device enters low-power stop mode. cmdvcc 1_8v 5v/3v stop mode off_ pres_ v cc_ deactivate interface activate stop mode deactivate stop mode 220 s delay off_ follows pres in stop mode off_ asserted to wait for delay 8ms debounce figure 8. stop-mode sequence
ds8005 smart card power select the device supports three smart card v cc voltages: 1.8v, 3v, and 5v. the power select is controlled by the 1_8v and 5v/ 3v signals as shown in table 3. the 1_8v signal has priority over 5v/ 3v . when 1_8v is asserted high, 1.8v is applied to v cc when the smart card is active. when 1_8v is deasserted, 5v/ 3v dictates v cc power range. v cc is 5v if 5v/ 3v is asserted to a logic- high state, and v cc is 3v if 5v/ 3v is pulled to a logic-low state. care must be exercised when switching from one v cc power selection to the other. if both 1_8v and 5v/ 3v are high with cmdvcc high at the same time, the device enters stop mode. to avoid accidental entry into stop mode, the state of 1_8v and 5v/ 3v must not be changed simultaneously. a minimum delay of 100ns should be observed between changing the states of 1_8v and 5v/ 3v . see figure 9 for the recom- mended sequence of changing the v cc range. smart card interface 16 ______________________________________________________________________________________ v cc select stop mode 1.8v 1.8v 3v 3v 5v 1_8v 5v/3v cmdvcc figure 9. smart card power select table 3. v cc select and operation mode 1_8v 5v/ 3v cmdvcc v cc select (v) card interface status 0 0 0 3 activated 0 0 1 3 inactivated 0 1 0 5 activated 0 1 1 5 inactivated 1 0 0 1.8 activated 1 0 1 1.8 inactivated 1 1 0 1.8 reserved (activated) 1 1 1 1.8 not applicablestop mode
switching a/b interfaces one of the device? key features is the ability to man- age two card slots at the same time. the multiplexing control signal sel_ab is used to determine which inter- face is active for communication, though it is possible to leave both interfaces powered at the same time. when switching between interfaces, the device pre- serves the state of control signals clkdiv1, clkdiv2, 1.8v, 5v/ 3v , cmdvcc , and rstin by latching the pin states. this allows the now inactive interface to stay powered while the other interface is activated for com- munication, and it also allows for fast switching between card interfaces without the need for a card deactivation and activation sequence. after switching sel_ab, the control signals clkdiv1, clkdiv2, 1.8v, 5v/ 3v , cmdvcc , and rstin must not be changed for 78? while the device latches the state of the pins for the inactive interface. after the control signals are latched, a 42? window is provided to change the control inputs. note that the behavior of the off and off2 pins is dependent on the sel_ab pin. off always refers to the active interface, and off2 always reports events on the inactive interface. this allows the device to monitor for card insertion and removal on both inter- faces simultaneously. see figure 10 for details on the behavior of the sel_ab, off , and off2 pins with regard to card presence. ds8005 smart card interface ______________________________________________________________________________________ 17 ds8005 transparent latch a reg a clka div v cca clka ena rsta, i/oa, gnda 1_8v, 5v/3v, clkdiv1, clkdiv2, rst, i/o sel_ab off transparent latch b reg b clkb div v ccb clkb presa ena rstb, i/ob, gndb transition sensor delay smart card status 1 presb smart card status 2 off2 1 0 1 0 figure 10. switching a/b interfaces
ds8005 smart card interface 18 ______________________________________________________________________________________ applications information performance can be affected by the layout of the appli- cation. for example, an additional cross-capacitance of 1pf between card reader contacts c2 (rst_) and c3 (clk_) or c2 (rst_) and c7 (i/o_) can cause contact c2 to be polluted with high-frequency noise from c3 (or c7). in this case, include a 100pf capacitor between contacts c2 and cgnd. application recommendations include the following: ensure there is ample ground area around the device and the connector; place the device very near to the connector; decouple the v dd and v dda lines sepa- rately. these lines are best positioned under the con- nector. the device and the host microcontroller must use the same v dd supply. pins clkdiv1, clkdiv2, rstin, pres_, i/oin, 5v/ 3v , 1_8v, cmdvcc , and off are referenced to v dd ; if pin xtal1 is to be driven by an external clock, also reference this pin to v dd . trace c3 (clk) should be placed as far as possible from the other traces. the trace connecting cgnd to c5 (gnd) should be straight (the two capacitors on c1 (v cc_ ) should be connected to this ground trace). avoid ground loops between cgnd and gnd. decouple v dda and v dd separately. if two supplies are the same in the application, they should be con- nected in a star on the main trace with all these layout precautions, noise should be kept to an acceptable level and jitter on c3 (clk_) should be less than 100ps. reference layouts are available on request. technical support for technical support, go to https://support.maxim- ic.com/micro .
ds8005 smart card interface ______________________________________________________________________________________ 19 package type package code document no. 28 so w28+1 21-0042 ds8005 maxq1103 100nf +3.3v +3.3v +3.3v 100k 100k 33pf 100nf* 220nf* *place a 100nf capacitor close to the ds8005 and place a 220nf capacitor close to card contact. 33pf clkdiv1 presa presb clkdiv2 5v/3v 1_8v rstin cmdvcc i/oin off2 pres gpio ... ... gpio iso_data off sel_ab gpio gpio gpio v cca rsta interface a clka i/oa rstb clkb i/ob cgnd xtal1 xtal2 gnd v dd 10 f v dda2 v dda 100nf 100nf* 220nf* v dd presb v ccb interface b typical application circuit package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to th e package regardless of rohs status.
ds8005 smart card interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release

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